1. Field
The present invention relates to via/contact etch rates in semiconductor chip design and manufacturing, and more particularly to determining the via/contact pattern density effect in via/contact etch rate.
2. Related Art
Using a plasma etch process to create vias in the manufacturing of semiconductor chips is known in the art. Typically, based on currently employed dual-damascene technology metal lines are deposited with the electroplating process step into a dielectric layer previously patterned in the plasma etch process step. A patterned photoresist layer is deposited on top of the interlayer dielectric (ILD). Where the ILD is not covered by the photoresist, etchant from the plasma etches a feature. One of the most common integration schemes used today for 90 nm and 65 nm technological nodes is referred to as dual-inlaid “Via First Trench Last” (VFTL), meaning the via structure is etched before the trench. Ideally, the via is etched until an opening reaches an etch stop layer (dielectric barrier) previously deposited on the top of underneath metal layer. This barrier is etched (open) at the very last step in this VFTL scheme when the trench was etched, photoresist was striped, and the organic was removed. However, sometimes a via is over-etched or under-etched, affecting wafer yield. In an under-etch, the etching process stops before it reaches the etch stop layer, and inadequate electrical contact results. In an over-etch, the etching process continues even after it reaches the etch stop layer. This results in via CD widening, which can be responsible for the underneath metal line side-wall erosion. A similar situation takes place with the contact etch. The only difference is employment of silicide layers as etch stop layers and the absence of the trench etch step in process flow. A variety of control techniques are used for detection of the etch stop point to avoid the over-etch/under-etch. Aa an example of this technique we can mention an optical emission spectroscopy. When etch profile reaches the underneath etch stop layer, or silicide layer in the case of the contact etch, a sensing device detects a trace concentration of specific molecules in the gas phase and the etch process is terminated. Existing variation in etch rate can result in the situation that some of the vias/contacts will be still under-etched while some other already over-etched when the etch is stopped.
Variations in via/contact etch rates can result in the over-etch and under-etch of vias/contacts. This can be due to non-uniform via/contact density patterns on a wafer. FIGS. 1A–1B are simplified diagrams of a via layout on a wafer surface and a cross-section of vias in a via-layer, respectively. As illustrated in FIG. 1A, the vias are not uniformly distributed across a layout, leading to the microloading effect, which means a depletion in reactive gas species, which are needed for surface etching reactions (etchant), in the wafer regions where a higher etchant consumption occurs due to the greater via/contact density. This happens because of a reactant transport (by means of gas phase diffusion and flow) limitations which do not allow alleviation of concentration gradients over the length scale of the via/contact density variations. Additional variations in via/contact etch rates come from the neighbor features competiting for etchant species. As illustrated in FIG. 1B, when vias are close together, their respective regions of the surrounding gas phase, which supply etchant species for etching reactions, may overlap. These regions are restricted by the line of sight forming the solid angle from which the plasma bulk can be observed from the via inside. Because of a ballistic nature of the reactant transport, which takes place at the typical gas pressures used for plasma etch, only reactant located inside this solid angle can reach a corresponding feature and participate in etching reactions. These vias, characterized by overlapped gas phase “supply” regions should “share” reactants, that results in further reduction in etch rate. Local configuration in vias/contacts location strongly influences this overlap resulting in enhanced variations in etch rates. Some specific fragments of the via/contact layout can be responsible for creation of a strong reactant flux depletion resulting in severe via/contact under-etch.
Accordingly, there exists a need for a method for determining the effect of via/contact pattern density in via/contact etch rate. By determining this effect, chip designers can check the layout design regarding elimination of hot spots responsible for a prospective via/contact under-etch and modify it to minimize via/contact failures. Similarly, chip manufacturers can modify the etching process to minimize via/contact failures. The present invention addresses such a need.